1. Field of the Invention
This invention relates to a flash memory, and particularly to a cell structure of a type wherein one of cells employed in a flash memory and each having a select transistor is composed of two transistors.
2. Description of the Related Art
Each of stack type memory cells employed in a flash memory has a merit that the number of transistors may be one per cell. Since a technique that is a direct extension of an ultraviolet erase type EPROM (Erasable Programmable Read Only Memory), is used, the stack type memory cells are able to become the mainstream of the present flash memory. A cross-sectional view of stack type memory cells will first be shown in FIG. 1. In FIG. 1, stack type transistors each formed by successively stacking a tunnel oxide 12, a floating gate 13, an ONO (Oxide-Nitride-Oxide) stacked insulating film 14 and a control gate 15 on one another are provided on a silicon semiconductor substrate 11. A drain diffusion layer 16 and a source diffusion layer 17 are formed in the surface of the silicon semiconductor substrate 11, which is provided in the vicinity of each stack type transistor. An interlevel insulating film 18 and a contact hole 19 defined in the interlevel insulating film 18 are provided on each stack type transistor and are connectable to the drain diffusion layer 16, for example, through a metal conductor or interconnect 20. A surface protection film 21 is formed on the metal interconnect 20.
FIG. 2 is a plan view showing the manner in which the stack type memory cell transistors are disposed in array form. A region surrounded by the dotted line corresponds to one memory cell. The same regions as those shown in FIG. 1 are identified by like reference numerals. A plurality of the control gates 15 are electrically connected to one another to form each of control lines 30. A plurality of the metal interconnects 20 on the drain diffusion layers 16 are electrically connected to one another so as to run perpendicular to the word lines 30 to form each of bit lines 31. Further, a plurality of the source diffusion layers 17 are electrically connected to one another so as to run parallel to the word lines 30 to form a common source diffusion-layer conductor or interconnect 32. FIG. 1 corresponds to a sectional view taken along line A-A' in FIG. 2. A method of writing data into each stack type memory cell and erasing it therefrom will now be described with reference to FIG. 3. When it is desired to write the data into the memory cell, 12 V, 6 V and 0 V are respectively applied to the control gate 15, the drain diffusion layer 16, and the source diffusion layer 17 and the silicon semiconductor substrate 11. Under such a bias condition, a channel current flows between the source and drain of each memory cell transistor and hot electrons generated in the neighborhood of the drain thereof are injected and stored in the floating gate 13. The writing of the data into the stack type memory cell is completed in this way. Such writing is called "channel hot electron writing, which is abbreviated as CHE writing". When it is desired to erase the data from the memory cell, -7 V, 5 V and 0 V are respectively applied to the control gate 15, the source diffusion layer 17 and the silicon semiconductor substrate 11 and the drain diffusion layer 16 is brought into a floating state. Thus, the data erasing is performed by drawing the electrons from the floating gate 13 to the source diffusion layer 17. Since the data erasing is performed using a Fowler-Nordheim tunneling current that flows through the tunnel oxide 12, such erasing is called "FN erasing" for short. Since the CHE writing needs a large current whereas the FN erasing needs a reduced amount of current, a required voltage can be generated from an on-chip internal boosting circuit.
A NAND type memory cell will now be described. The NAND type memory cell has an advantage that since each contact hole 19 is unnecessary although one cell is made up of one transistor as in the case of the stack type memory cell, each NAND type memory cell can be made smaller and increased in capacity. Both of NAND type writing and erasing are performed using the Fowler-Nordheim tunneling current (FN writing and erasing) and hence a required write and erase voltage can be generated from an internal boosting circuit.
A FLOTOX (Floating gate Tunnel Oxide) type memory cell disclosed in a technical literature (IEEE International Solid State Circuit Conference Dig. Tech. 1980, pp 152-153, 271) is of a type wherein a tunnel oxide region is formed only in a portion of a lower part of a floating gate. The tunnel oxide region is formed on a drain diffusion layer. Since both writing and erasing are of the FN writing and erasing, a required write and erase voltage can be produced by an internal boosting circuit. Further, since the FLOTOX type memory cell has select transistors, a range for controlling a threshold value of each memory cell is wider than that of each of the stack type and NAND type memory cells as will be described later.